ICs, LLC Radiation-tolerance technologies for space electronics

ICs technology

Technologies

ICs is increasingly focused on the underlying circuit technologies that enable radiation-tolerant electronics. Two major areas organize this work: Radiation Hard By Design technologies and Asynchronous Sequential Circuits. These areas are distinct but related: ICs’ asynchronous sequential circuit work stands on its own while also underpinning newer generations of Self-Restoring Logic.

Radiation tolerance

Radiation Hard By Design

RHBD is the umbrella for ICs circuit technologies that address radiation tolerance through the design of the circuitry itself. Technologies under this umbrella include Self-Restoring Logic and the earlier SERT approach. ICs' current emphasis is on the underlying technologies that enable radiation-tolerant implementations rather than on any single packaged device.

Self-Restoring Logic (SRL) Radiation-tolerant logic with multiple generations of ICs development

Self-Restoring Logic is an ICs RHBD technology developed to tolerate single-event upsets (SEUs). SRL uses asynchronous internal feedback and does not rely on the voter circuits used in traditional Triple Modular Redundancy (TMR). ICs has developed multiple generations of SRL, with newer work drawing on the company's asynchronous sequential circuit design foundation.

ICs has applied SRL in custom space ICs and in a commercial RHBD implementation. ICs also partnered in an SRL synthesis-library effort used to support RHBD chip design in a commercial foundry.

Selected SRL references

  1. E. Cameron, G. Maki, L. Miles, J. Feeley, and S. Whitaker, “High-Speed High-Density Fault Tolerant Electronics,” 2024 IEEE Aerospace Conference, February 2024.
  2. L. Miles, E. Cameron, S. Whitaker, G. Maki, J. Feeley, and M. Shreve, “Single Event Upset in High-Speed Circuitry: Comparing Legacy Flip-Flops with Self-Restoring Logic,” Journal of Radiation Research and Engineering, Vol. 34, 2018.
  3. S. Whitaker and G. Maki, “Self Restoring Logic Structures,” U.S. Patent 11,626,403, issued April 11, 2023.
  4. S. Whitaker and G. Maki, “Self Restoring Logic Structures,” U.S. Patent 11,552,079, issued January 10, 2023.
  5. S. Whitaker and G. Maki, “Self Restoring Logic Structures,” U.S. Patent 11,069,683, issued July 20, 2021.
  6. S. Whitaker and G. Maki, “Self Restoring Logic,” U.S. Patent 8,081,010, issued December 12, 2011.
SERT Earlier ICs Radiation Hard By Design technology

SERT is an earlier ICs RHBD technology and part of the company's radiation-tolerant design heritage.

Sequential circuit design

Asynchronous Sequential Circuits

Asynchronous Sequential Circuits (ASC) are a technology area in their own right. ICs' work in this field spans decades of research in safe, reliable, fault-tolerant, and self-synchronized sequential circuits. That body of work also underpins newer SRL development.

Research and design foundation Longstanding ICs work in asynchronous sequential circuit theory and implementation

ICs researchers have published on asynchronous sequential circuit design over many decades, including work on safe asynchronous circuits, fault-tolerant machines, reliable sequential circuits, pass-transistor implementations, and self-synchronized VLSI circuits.

Dr. Gary Maki has also taught asynchronous sequential design theory at the undergraduate and graduate level for more than 30 years at the University of Idaho and the University of New Mexico.

Selected asynchronous-design publications

  1. S. Whitaker and G. Maki, “Self Synchronized Asynchronous VLSI Circuits,” IEEE Transactions on Computers, Vol. 41, 1992.
  2. S. Whitaker and G. Maki, “Pass Transistor Asynchronous Sequential Circuits,” IEEE Journal of Solid-State Circuits, 1989.
  3. G. Maki, “The Design of Reliable Sequential Circuits,” IEEE Circuits and Systems Journal, Vol. 7, 1975.
  4. G. Maki and D. Sawin, “Fail Safe Asynchronous Sequential Machines,” IEEE Transactions on Computers, 1975.
  5. G. Maki and D. Sawin, “Fault Tolerant Asynchronous Sequential Machines,” IEEE Transactions on Computers, 1974.
  6. G. Maki and R. Wickersham, “Safe Asynchronous Sequential Circuits,” IEEE Transactions on Computers, 1974.
  7. G. Maki and D. Sawin, “Asynchronous Sequential Machines Designed for Fault Detection,” IEEE Transactions on Computers, 1974.
  8. G. Maki and J. Tracey, “Generation of Design Equations in Asynchronous Sequential Circuits,” IEEE Transactions on Computers, 1969.
Continuing development Hazard identification, scalable design methods, synthesis, and verification

Current ICs research includes identifying hazards that can produce critical races in legacy sequential-circuit designs, developing methods to detect those hazards, and developing design procedures intended to prevent them in future implementations.

A second direction addresses scalability. Traditional asynchronous sequential circuit design methods work well for small circuits but become difficult as state complexity grows. ICs is developing design approaches intended to support larger flow tables and more complex asynchronous designs.

The longer-term research direction is to expand the practical role of asynchronous sequential circuits in digital design, supported by new design procedures and synthesis tools.

Design, synthesis, and verification tools Specialized tools developed to support ICs circuit design and verification
NOVA
An event-driven logic simulator developed and used by ICs for custom integrated-circuit design over many years, with use extending beyond ICs.
SRL circuit verification
Specialized verification used to help confirm that physical implementation preserves the intended radiation-tolerant behavior of SRL-based designs.
Custom VLSI verification models
Specialized models used to compare expected equation-derived behavior with outputs from custom chip designs during the design-verification process.