DWT Processor (X025)

The Discrete Wavelet Transform (DWT) chip implements a three-level, two-dimensional discrete wavelet transform on an image input in a simple line-by-line format. The complete algorithm is outlined in CCSDS 122.0-B-1.

Highlights

• Implements 9/7 Integer and 9/7 Real DWT
• 20 Mpixels/s data rate at 100 MHz
• Parallel 16-bit input
• 24-bit two’s-complement parallel output
• TID > 100 krad
• SEL immune to 120 MeV·cm²/mg LET
• 2.5 V core voltage
• 256-pin ceramic QFP (244 pins used)

Description

The DWT implements a three-level, two-dimensional discrete wavelet transform on an image input in a simple line-by-line format. The exact algorithm is outlined in CCSDS 122.0-B-1. The compression system is based on the DWT, the BPE, and SRAM chips.

The DWT contains six major blocks: the external memory interface, main control block, output block, serial interface, vertical and horizontal processors, and MAC (multiply-accumulate). The basic operation of the chip consists of two modes: configuration and processing.

The chip can be configured after reset and before any data is sent. The easiest way to configure the chip is to set Default to either 9/7 Integer (1) or 9/7 Real (0), reset the chip, use the serial interface to program width, height, and output address, and then start inputting data. Once any data is sent, the chip enters processing mode. The only way to return to configuration mode is via a reset. Once configured, data is sent in a line-by-line fashion through the parallel data interface. For in-depth algorithm details, refer to the CCSDS documentation and the product specification.